1. Field of the Invention
The present invention relates to a BiCMOS semiconductor device and to a process for fabricating the same. In particular, the present invention relates to a BiCMOS type semiconductor device comprising a resistance and a capacitance formed by a bipolar transistor, a MOS (metal oxide semiconductor) transistor, and a desired conductor film formed on the same substrate. The present invention also relates to a process for fabricating said device. In the present specification, the term "BiCMOS semiconductor device" refers collectively to semiconductor devices having both a bipolar transistor and a MOS transistor.
2. Prior Art
With increasing demand on higher performance and larger scale of integration, advanced LSIs furnished with both advantages of CMOS and BIPs (bipolar transistors) are attracting more attention. A BiCMOS LSI not only has the merits of a CMOS capable of realizing high integration (packing density) and low power consumption, but also has the superiority of BIP, i.e., high speed. In the field where LSIs of higher performance are required, in particular, it is essential to integrate the most advanced MOS technology and BIP technology. The trend in such advanced fields is, accordingly, employing a so-called LDD (lightly doped drain) structure for the MOS structure, and a so-called double polysilicon structure for the BIP structure.
Referring to FIGS. 2 to 4, the structure of two representative types of MIS (metal insulator semiconductor) capacitance are described below.
The structures illustrated in FIGS. 2 and 3 both comprise a first layer A1 (aluminum) 19 as the upper electrode and an N-type plug 13 (see FIG. 2) or a combination of an N-type plug 17 with an N-type BL (buried layer) 13 (see FIG. 3) as the lower electrode. A dielectric film (Si.sub.3 N.sub.4) 16 or 26 is incorporated in the structure. In this type of structure, noise, etc., ascribed to the fluctuation in substrate potential due to, e.g., the substrate current of digital MOS, directly affects the MIS capacitance through the N-type region.
In contrast to the above structure, another related art structure as illustrated in FIG. 4 comprises an impurity-doped polysilicon 33 on a field oxide film as the lower electrode. The MIS capacitance in this type of structure can be thereby maintained indifferent to the fluctuation in substrate potential. This time, however, the frequency characteristics of the MIS capacitance is impaired because the resistance of the polysilicon electrode 33 is too large. A MIM (metal insulator metal) structure using a metal such as aluminum is preferred for the lower electrode of the structure shown in FIG. 4, however, it is difficult to form a high quality thin film 34 of a dielectric such as Si.sub.3 N.sub.4, because a high temperature over the melting point of aluminum, i.e., a temperature in the range of from 700.degree. to 800.degree. C., is necessary to deposit a dense Si.sub.3 N.sub.4 film by CVD. A MIM structured lower electrode can be realized by using a refractory metal or a silicide thereof, such as W (tungsten) or WSi.sub.x. However, thin films of these materials have inferior adhesibility to an insulator film, and they have poor affinity with a Si.sub.3 N.sub.4 film having large tensile stress. Those shortcomings can be overcome only at the expense of increased process steps, and this is not necessarily practical. The above problems apply not only to a MIS capacitance but also to a MOS capacitance.
FIG. 5 illustrates a fourth type of a related art showing a representative MIS capacitance. The process steps for fabricating a related art BiCMOS LSI are explained in detail referring to FIGS. 5 to 8. In FIG. 8 are given cross sectional views of the upper portion on a silicon substrate, comprising a double polysilicon structured bipolar transistor portion Tr1 and a P-channel MOS transistor portion Tr2.
Referring to FIG. 5A, a buried N.sup.+ layer 47 and a diffusion layer are formed for a substrate 41, in the area for establishing the bipolar transistor portion Tr1. The buried layer 47 and the diffusion layer function as a contact for collector of an NPN transistor.
After forming a 400 to 500 nm thick LOCOS oxide film 57 and a P.sup.+ diffusion layer 53 for element isolation, a 10 to 20 nm thick insulator film 41 is formed as a gate oxide film for the MOS transistor.
A polysilicon film from about 100 to 200 nm in thickness is deposited over the entire surface of the resulting structure by CVD. This film serves as a electrically conductive film 42. Openings corresponding to a base and an emitter forming portion are then perforated in the layered polysilicon/gate oxide film by a known dry etching technology.
The polysilicon film (the electrically conductive film 42) functions as a protective film for the gate oxide film during the formation of an opening. Hence, the polysilicon film prevents failure of withstand voltage due to pollution of the gate oxide film from occurring in the step of resist removal during the formation of the opening in the gate oxide film.
Referring to FIG. 5B, a 100 to 200 nm thick polysilicon film is then deposited by CVD to obtain a second electrically conductive film 44. Taking the previously CVD-deposited polysilicon film (conductive film 42) into account, a polysilicon film from 300 to 400 nm in total thickness is formed.
Subsequently, N.sup.+ ions are ion-implanted into the gate contact region of the MOS transistor portion. After ion-implanting P.sup.+ ions into the base contact forming region of the bipolar transistor portion, the layered polysilicon layer above (the first and second conductive films 42 and 44) is processed by a conventional dry etching technology except for the gate contact of the MOS transistor portion and the base contact of the bipolar transistor portion. Then, ion-implantation of P.sup.- ions is performed to form an LDD diffusion layer 54 in the MOS transistor portion.
A 200 to 400 nm thick SiO.sub.2 film is deposited by CVD and then anisotropically etched by a known dry etching technology to form a sidewall-like SiO.sub.2 spacer 56 for an LDD.
The base and emitter forming regions of the bipolar transistor can be protected from overetching because they are covered with polysilicon during the anisotropic etching in forming the SiO.sub.2 spacer for the LDD. Accordingly, the element can be obtained free of problems such as element degradation due to RIE (reactive ion etching) damage and decrease in product yield. The MOS transistor portion is then subjected to ion-implantation of P.sup.+ ions to form a source and drain diffusion layer 55.
Referring to FIG. 5C, a 300 to 400 nm thick SiO.sub.2 is deposited by CVD, and the layered SiO.sub.2 /polysilicon film of the base and emitter regions of the bipolar transistor is removed by a known dry etching technology.
An SiO.sub.2 film is deposited to a thickness of from 400 to 600 nm is deposited by CVD, and subjected to anisotropic etching by a known dry etching process to form an SiO.sub.2 spacer 58 for the isolation of emitter and base contacts. A polysilicon film 41 for forming an emitter is deposited by CVD, and processed by a known dry etching technology. Base and emitter are then formed by implanting and diffusing ions into said polysilicon film.
P.sup.+ ions are diffused from the base take out electrode to form a graft base at the same time the source and drain diffusion layer of the MOS transistor is activated by the heat treatment.
Referring to FIG. 5D, a 300 to 400 nm thick SiO.sub.2 film is deposited by CVD to establish an insulator film 45. Then, each of the electrodes (not shown in the figure) is formed by a known interconnection technology. The bipolar transistor portion Tr1 comprises a base Base, an emitter Em, and a collector Col, and the MOS transistor portion Tr2 comprises contact portions S and D for source and drain, respectively.
A MIS capacitor using SiN as the dielectric is promising from the viewpoint of its applicability to an Active Pull-down circuit and the like. Special notice is presently taken of an Active Pull-down circuit as a technology which realizes a low power consuming high speed bipolar ECL (emitter coupled logic) gate. Since a high precision capacitance should be added to a conventional type BiCMOS LSI for the implementation of the Active Pull-down circuit, the use of a MIS capacitor having a large capacitance per unit of area and a favorable controllability is preferred.
A related art process for fabricating a BiCMOS LSI having an additional capacitance of high precision is described referring to FIGS. 6A to 6C. FIGS. 6A to 6C show the cross sectional view of a MIS capacitor portion T1 and a P-channel MOS transistor portion T2 both formed on the upper side of a silicon substrate.
Referring to FIG. 6A, an N.sup.+ diffusion layer 67 is formed on the substrate forming a MIS capacitor T1 (sometimes referred to simply hereinafter as a "MIS capacitor T1 forming portion").
Referring to FIG. 6B, an insulator film (SiO.sub.2) 61 of the MIS capacitor T1 forming portion is removed by a known dry etching process. Then, a 30 to 60 nm thick SiN is deposited by CVD, and processed by a known dry etching technology to leave over SiN as a dielectric film 63 on the MIS capacitor T1 forming portion.
Referring to FIG. 6C, a 300 to 400 nm thick SiO.sub.2 film is deposited by CVD to provide an insulator film 65. Then, each of the electrodes (not shown in the figure) is formed by a conventional interconnection technology.
The conventional process for fabricating a BiCMOS LSI having an additional high precision capacitance as described in the foregoing, however, suffers the following problems:
(1) A step must be newly added to the process for forming the MIS capacitor, because the insulator film on the MIS capacitor forming region must be removed by etching (see FIG. 6B); and
(2) The contact on the SiN constituting the MIS capacitor must be formed separately from the other contacts in the contact forming step (see FIG. 6C). Since a conventional dry etching technology does not support an etching condition which realizes SiO.sub.2 etching at a high selectivity ratio with respect to SiN, the opening on the SiN for a contact must be formed by wet etching using an hydrofluoric acid based solution. Such an etching process is not suited for fine processing.
A process for fabricating a BiCMOS LSI is described in detail referring to FIGS. 7 to 10. FIGS. 7 to 10 show the cross sectional view of double polysilicon structured bipolar transistor and a P-channel MOS transistor portion both formed on the upper portion of a silicon substrate.
Referring to FIG. 7A, a buried N.sup.+ layer 82 and a diffusion layer are formed in the bipolar transistor portion of a substrate 81. The buried layer 82 and the diffusion layer function as a contact for collector of an NPN transistor.
After forming a 400 to 500 nm thick LOCOS oxide film 83 and a P.sup.+ diffusion layer 84 for element isolation, a 10 to 20 nm thick insulator film 85 is formed as a gate oxide film.
A first polysilicon layer 86 from about 100 to 200 nm in thickness is then deposited over the entire surface of the resulting structure by CVD. Openings corresponding to a base and an emitter forming portion are then perforated in the layered polysilicon 86/gate oxide film 85 by a known dry etching technology.
The polysilicon film 86 functions as a protective film for the gate oxide film 85 during the formation of the opening. Hence, the polysilicon film prevents failure of withstand voltage due to pollution of the gate oxide film from occurring in the step of resist removal during the formation of the opening in the gate oxide film.
Referring to FIG. 7B, a 100 to 200 nm thick second polysilicon layer 87 is then deposited by CVD. This layer together with the previously CVD-deposited polysilicon film 86 gives a polysilicon film 300 to 400 nm in total thickness.
Subsequently, N.sup.+ ions are ion-implanted into the gate contact region of the MOS transistor portion. After ion-implanting P.sup.+ ions into the base contact forming region of the bipolar transistor portion, the layered polysilicon layer 87 above is processed by a conventional dry etching technology except for the gate contact of the MOS transistor portion and the base contact of the bipolar transistor portion.
Then, ion-implantation of P.sup.- ions is performed to form an LDD diffusion layer 88 in the MOS transistor portion.
A 200 to 400 nm thick SiO.sub.2 film is deposited by CVD and then anisotropically etched by a known dry etching technology to form a sidewall-like SiO.sub.2 spacer 89 for an LDD.
The base and emitter forming regions of the bipolar transistor can be protected from overetching because they are covered with polysilicon during the anisotropic etching for forming the SiO.sub.2 spacer 89 for the LDD. Accordingly, the element can be obtained free of problems such as element degradation due to RIE (reactive ion etching) damage and decrease in product yield. The MOS transistor portion is then subjected to ion-implantation of P.sup.+ ions to form a source and drain diffusion layer 90.
Referring to FIG. 7C, a 300 to 400 nm thick SiO.sub.2 is deposited by CVD, and the layered SiO.sub.2 91/polysilicon film 87 of the base and emitter forming regions of the bipolar transistor is removed by a known dry etching technology.
An SiO.sub.2 film is deposited to a thickness of from 400 to 600 nm by CVD, and subjected to anisotropic etching by a known dry etching process to form an SiO.sub.2 spacer 92 for the isolation of emitter and base contacts.
A polysilicon film 93 for forming an emitter is deposited by CVD, and processed by a known dry etching technology. A base 95 and an emitter 94 are then formed by implantation and diffusion of ions into said polysilicon film. P.sup.+ ions are diffused from the base contact to form a graft base 96 at the same time the source and drain diffusion layer 90 of the MOS transistor is activated by the heat treatment.
Referring to FIG. 7D, a 300 to 400 nm thick SiO.sub.2 film 97 is deposited by CVD to establish an insulator film 45. Then, each of the electrodes (not shown in the figure) is formed by a known interconnection technology.
Referring to FIG. 8, a seventh type of a related art structure is described below.
A MIS capacitor using SiN as the dielectric is promising from the viewpoint of its applicability to an Active Pull-down circuit and the like. Since special notice is taken of an Active Pull-down circuit as a technology which realizes a low power consuming high speed bipolar ECL (emitter coupled logic) gate, it is demanded that a high precision capacitance be added to a conventional type BiCMOS LSI for the implementation of the Active Pull-down circuit. Accordingly, the use of a MIS capacitor having a large capacitance per unit of area and a favorable controllability is preferred.
A related art process for fabricating a seventh related art BiCMOS LSI equipped with an additional high precision capacitance is described referring to FIGS. 8A to 8C. FIGS. 8A to 8C show the cross sectional view of a MIS capacitor portion and a P-channel MOS transistor portion T2 both formed on the upper side of a silicon substrate.
Referring to FIG. 8A, an N.sup.+ diffusion layer 102a is formed on the MIS capacitor forming portion.
Referring to FIG. 8B, an SiO.sub.2 film 111 of the MIS capacitor forming portion is removed by a known dry etching process.
Then, a 30 to 60 nm thick SiN is deposited by CVD, and processed by a known dry etching technology to leave over SiN as a dielectric film 118 on the MIS capacitor forming portion.
Referring to FIG. 8C, a 300 to 400 nm thick SiO.sub.2 film is deposited by CVD to provide an insulator film. Then, each of the electrodes (not shown in the figure) is formed by a conventional interconnection technology.
FIG. 9A shows a cross sectional view for the principal portion (the portion relating to the device according to the present invention) of an eighth type of a related art BiCMOS semiconductor device. Referring to FIG. 9, the device comprises a P-type substrate (having a resistivity of about 10 .OMEGA..cm) 121, a buried N.sup.+ layer (containing diffused Nb and having a resistivity of about 20 .OMEGA..m) 122, an N-type epitaxially grown layer (about 1 .OMEGA..m in resistivity) 123, a P-type well layer 124, an N-type well layer 125, a LOCOS oxide film 126 about 500 nm in thickness, a first polysilicon layer (about 400 nm in thickness) 127 for forming a MOS gate, a P.sup.+ layer 129 for forming source and drain regions for PMOS transistor, a P.sup.+ base contact layer 129, a SiO.sub.2 insulator film 130 having deposited by CVD using TEOS to a thickness of about 100 nm, a second polysilicon layer 131 about 70 nm in thickness to provide a polysilicon emitter, a second polysilicon layer 131 about 70 nm in thickness to give a polysilicon resistor, a BPSG reflow treated film 132 about 600 nm in thickness, and an aluminum connection 133.
A prior art BiCMOS semiconductor device is fabricated by the following process steps:
diffusing Sb inside a P-type substrate 121, followed by forming a buried N.sup.+ layer 122; PA1 epitaxially growing an N-type epitaxial layer 123; PA1 oxidizing to form a 50 nm thick oxide layer; forming a mask pattern having a so-called "window" in the P-well forming region, and introducing boron by ion implantation to form a P-well; PA1 forming in a similar manner as the previous step, an N-well by opening a window in the N-well forming region and introducing phosphorus by ion implantation; PA1 subjecting the well to impurity diffusion to establish a P-well layer 124 and an N-well layer 125; PA1 depositing an Si.sub.3 N.sub.4 film by CVD to provide a masking layer against oxidation; PA1 patterning the masking layer for LOCOS process, followed by oxidation to form a LOCOS oxide film 126; PA1 after removing the Si.sub.3 N.sub.4 masking layer, forming a gate oxide film; PA1 forming a polysilicon gate; PA1 subjecting the structure to ion implantation at a BF.sub.2 dose of about 10.sup.14 to form Base; PA1 performing ion implantation at a BF.sub.2 dose of about 10.sup.16 to form a P.sup.+ layer; PA1 depositing an SiO.sub.2 layer by CVD using TEOS, to thereby obtain an insulator film 130; PA1 perforating an emitter forming region; PA1 depositing a second polysilicon layer by CVD; PA1 introducing arsenic at a dose of about 10.sup.16 into the polysilicon region of the emitter by ion implantation; PA1 introducing arsenic or phosphorus into the polysilicon resistor region at a dose of about 10.sup.14 by ion implantation; PA1 patterning the polysilicon layer; PA1 depositing BPSG by CVD; PA1 providing an opening for contacts; PA1 subjecting the structure to reflow treatment at 900.degree. C. for a duration of 20 minutes to activate the base region and the P.sup.+ layer; and PA1 forming an aluminum connection.
Referring to the nineteenth step of a related art process above for fabricating a semiconductor device, the insulator layer to be perforated for the contacts on a polysilicon layer is a BPSG film merely 600 nm in thickness. This layer is relatively thinner than the other regions in which a 600 nm thick BPSG and a 100 nm thick film from TEOS, i.e., a film with a total thickness, are formed. Accordingly, the insulator layer of the polysilicon layer tends to be more deeply etched than the layer on the other portions. When the etching of contact is performed by an RIE process, for instance, the duration of etching is generally set as such that an additional margin of 50% may be included in the step to thereby obtain a sufficiently wide opening in the transistor region having a 700 nm thick coating. Thus, by a simple calculation: EQU 700.times.1.5-600.apprxeq.450 nm,
an overetching thickness as reduced to an oxide film of about 450 nm may result. Even if an etching rate ratio for polysilicon to SiO.sub.2 of 1/10 were to be assured, a polysilicon film from 25 to 70 nm in thickness results from the etching. Then, such a thin polysilicon film is no longer reliable as a contact. The resulting structure of the contact portion A in a polysilicon resistance shown in FIG. 9A is illustrated in further detail in FIG. 9B.
The following three measures are proposed to overcome the aforementioned problem, however, they are not practically feasible because of the attached reasons.
(1) A first measure comprises changing the etching condition as such that the ratio of the etching rate for polysilicon to that for SiO.sub.2 may be greater. The etching rate ratio, however, is fundamentally limited so long as the etching is performed using the RIE process. Moreover, such a measure also is problematic because other characteristics which should be controlled are impaired; i.e., problems such as the decrease in etching rate, and the degradation of the contact hole shape newly occur.
(2) A second measure comprises employing other process methods based on chemical reactions, such as plasma etching and solution etching. These methods, however, are for isotropic etching, and are not suited for fine processing.
(3) A third measure comprises thickly forming a polysilicon film for the resistor. This measure, however, fails to realize high resistance.